A self-checking cell logic block for fault tolerant FPGAs
نویسندگان
چکیده
This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-UpTable @UT) and a D FlipFlop. The CLB is designed using pass-transistor-based multiplerers, either to select the output of the Cinput Lm, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a semor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection ofany single transistor fault.
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